The invention relates to programming a nonvolatile memory cell comprising a diode in series with an antifuse or other state change element.
Large integrated circuit memory arrays may comprise a large number of memory cells arranged in an array. The array may be flat rectangular or it may be 3-dimensional, in which multiple layers of rectangular arrays of memory cells are formed in a vertical stack. The memory cells may each comprise a high resistance material such as an antifuse or chalcogenide, which may be programmed to a low resistance state. In the case of an antifuse, the memory is one-time programmable and once the low resistance state is entered, it is not reversed. In the case of a chalcogenide, the state may be returned to high resistance (the memory cell may be un-programmed). For more selective programming, the memory cell commonly also comprises a diode for better controlled selection of the memory cell to be programmed.
In order to program a memory cell, voltages are typically applied to word and bit lines that contact opposite ends of the memory cell, causing current to pass through the memory cell for programming.
When a memory cell including a diode is to be programmed through word and bit lines connected to the memory cell, it is known to apply a programming voltage in the forward direction of the memory cell diode, and to apply compensating voltages to word and bit lines contacting memory cells not to be programmed. See Kleveland, et al., U.S. Pat. No. 6,816,410 entitled “METHOD FOR PROGRAMMING A THREE-DIMENSIONAL MEMORY ARRAY INCORPORATING SERIAL CHAIN DIODE STACK” issued Nov. 9, 2004 and owned by Matrix Semiconductor, Inc. Also see Kleveland and Knall U.S. Pat. No. 6,784,517 entitled “THREE-DIMENSIONAL MEMORY ARRAY INCORPORATING SERIAL CHAIN DIODE STACK” (Knall is the inventor of the present invention), and commonly assigned to Matrix Semiconductor, Inc.
It is desirable to improve the reliability of memory cell programming and to reduce power consumption as compared to such prior art methods.